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AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
SVC/SVD
SVC/SVD
(PRO = OPEN)
BUS IDLE
BUS IDLE
SVC/SVD INPUTS DISABLED
2-BIT BOOT VID
BUS IDLE
BUS IDLE
V CORE0
(CORE0 TARGET)
(CORE1 TARGET)
V CORE1
(NBV_BUF TARGET)
V NBV_BUF
PGD_IN
PWRGD
BLANK
HIGH IMPEDANCE
20 μ s
20 μ s
NOTE: MAX17009 IS IN SKIP MODE.
CORE0 IS LIGHTLY LOADED.
CORE1 IS HEAVILY LOADED.
Figure 7. PGD_IN Timing Figure
t ( SMPS ? SHDN ) =
t ( NBV _ BUF ? SHDN ) =
Shutdown
When SHDN goes low, the MAX17009 enters the low-
power shutdown mode. PWRGD is pulled low immedi-
ately, and the SMPS output voltages ramp down at
1mV/μs, while the NBV_BUF output slews at a rate set
by R TIME . At the end of the soft-shutdown sequence,
DL_ is kept low, and the 10 Ω switches from CSL_ to
GND are enabled, holding the outputs low:
V OUT
( 1 mV / μ s )
V NBV _ BUF R TIME C NBV _ BUF
( 7 μ A × 143 k Ω )
Slowly discharging the output capacitors by slewing the
output over a long period of time keeps the average
negative inductor current low (damped response), there-
by eliminating the negative output-voltage excursion that
occurs when the controller discharges the output quick-
ly by permanently turning on the low-side MOSFET
(underdamped response). This eliminates the need for
the Schottky diode normally connected between the out-
put and ground to clamp the negative output-voltage
excursion. The MAX17009 shuts down completely—the
drivers are disabled, the reference turns off, and the
supply currents drop to about 1μA (max)—20μs after
the controller reaches the 0V target. When a fault condi-
tion —overvoltage or undervoltage —occurs on one
SMPS, the other SMPS and the NBV_BUF immediately
go through the soft-shutdown sequence. To clear the
fault latch and reactivate the controller, toggle SHDN or
cycle V CC power below 0.5V.
Soft-shutdown for the NB regulator is determined by the
particular NB regulator’s shutdown behavior. In the typ-
ical application, the NB regulator’s SHDN pin or enable
pin is toggled at the same time as the MAX17009’s
SHDN pin.
32
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